1. Technical Field
The present invention relates to a circuit for resetting when a supply voltage appears, generally called xe2x80x9cPower-On-Resetxe2x80x9d circuit or xe2x80x9cPORxe2x80x9d circuit in the Anglo-Saxon terminology.
2. Description of the Related Art
When powered on, most of the programmed or programmable type logic circuits, in particular microprocessors, must be set in a zero state or RESET state in order to assure that their constitutive elements do not present undetermined logic states. The POR circuits, provided for this, deliver RESET signal when the supply voltage rises and reaches a first switching threshold Vth1, and release the RESET signal when the voltage reaches a second switching threshold Vth2. According to the chosen convention, the active value of the RESET signal may be 1 or 0. The release of the RESET signal corresponds to its setting to 0 in the first case and to its setting to 1 in the second case.
A difficulty in the design of a POR circuit, in particular in CMOS technology, is to obtain a release threshold Vth2 of the RESET signal which is constant and little sensitive to the sizes of the MOS transistors, in particular the ratio W/L between the width W and the length L of the gate of the transistors. This ratio is indeed likely to vary unintentionally, from a circuit to another, because of tolerances of the manufacturing method.
Another difficulty is to obtain a release threshold Vth2 of the RESET signal which is little sensitive to the temperature of the circuit.
FIG. 1 shows the electrical diagram of a conventional circuit POR1 supplied by a voltage VDD. In this diagram, the references of the PMOS transistors begin with a letter xe2x80x9cPxe2x80x9d and the references of the NMOS transistors begin with a letter xe2x80x9cNxe2x80x9d. The NMOS transistors have a threshold voltage VTN and the PMOS transistors have a threshold voltage VTP.
The circuit POR1 comprises a polarisation stage comprising, arranged in series, a ballast transistor PM1 (comparable to a resistance) and a diode transistor NM2, transistor PM1 having its gate connected to ground and transistor NM2 having its gate fed back to its drain. The mid-point of the transistors PM1, NM2 delivers a voltage V1 applied to the gates of two other transistors PM3, NM4 arranged in series, forming a switching stage. The mid-point of transistors PM3, NM4 delivers an output voltage V2 of the circuit POR1. The active state of the RESET signal being here by convention a logical xe2x80x9c1xe2x80x9d, the output voltage V2 is applied to the input of an inverting gate INV1 formed by two other transistors PM5, NM6, whose output delivers the RESET signal.
When the voltage VDD appears, the voltage V1 copies the voltage VDD as long as the diode transistor NM2 is OFF. The first switching threshold Vth1 is reached when the voltage VDD becomes equal to the threshold voltage VTN. The diode transistor NM2 and the transistor NM4 turn ON, the voltage V2 passes to 0 (ground GND) and the RESET signal passes to 1.
The second switching threshold Vth2, or release threshold of the RESET signal, is reached by the voltage VDD when the source-gate voltage VSG of transistor PM3 becomes equal to its threshold voltage VTP, the transistor PM3 turning ON. The voltage V1 at the terminals of the diode transistor NM2 being at this moment equal to:
V1=VTN+rixe2x80x83xe2x80x83(1)
r being the series resistance of transistor NM2 and i the current passing through it, the switching threshold Vth2 is thus equal to:
VDD=Vth2=VTP+V1=VTP+VTN+rixe2x80x83xe2x80x83(2)
In practice, the threshold voltages VTN and VTP are in the order of 0.8 V, and the voltage ri is in the order of 0.6 V. The switching threshold Vth1 is thus in the order of 0.8 V and the switching threshold Vth2 is in the order of 2,2 V at ambient temperature. As it can be seen in FIG. 2, the voltage of 0.8 V corresponds to a logic xe2x80x9c1xe2x80x9d of the RESET signal at a moment when this signal is set to 1 and the voltage of 2,2 V corresponds to a logic xe2x80x9c1xe2x80x9d of the RESET signal at a moment when it is brought back to 0 by the turning ON of transistor PM3.
The relation (2) shows that the switching threshold Vth2 depends on the threshold voltages VTN and VTP, as well as on the resistance r of the diode transistor NM2 and the current i flowing through the polarization stage. However, the threshold voltages VTP or VTN of MOS transistors are sensitive to temperature and increase when temperature decreases. Also, the resistance r of diode transistor NM2 depends on the ratio W/L of the gate of transistor NM2 and the current i depends on the ratio W/L of the gate of the ballast transistor PM1, which determines the electric resistance of this transistor.
The switching threshold Vth2 is thus sensitive to the ratio W/L of the gates of the switching stage transistors and to the temperature of the circuit.
The present invention is directed to overcome this drawback.
More particularly, a first object of the present invention is to provide a POR circuit which presents a switching threshold Vth2 not much sensitive to the ratio W/L of the gates of the MOS transistors.
A second object of the present invention is to provide a POR circuit which presents a switching threshold Vth2 not much sensitive to variations of temperature.
The foregoing objects are achieved as is now described. To that effect, the present invention provides a circuit for delivering a logic signal at the appearance of a supply voltage, comprising means for connecting an output node of the circuit to ground when the supply voltage reaches a first switching threshold, and means for connecting the output node to the supply voltage when the supply voltage reaches a second switching threshold, wherein the means for connecting the output node to the supply voltage comprise a switching transistor whose gate is polarized by a reference voltage taken at the terminals of a first precision resistance traversed by a current delivered by a current generator.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.